1. Field of the Invention
The present invention relates to a liquid crystal display apparatus, and more specifically, to a liquid crystal display apparatus having a gate insulating field effect transistor in each pixel.
2. Description of the Background Art
As a display panel for a personal computer, a television receiver, a mobile phone, and a personal digital assistant, a liquid crystal display apparatus having liquid crystal elements as display pixels is used. Such a liquid crystal display apparatus is effective in reducing power consumption, size and weight, as compared to a conventional type.
The display luminance of a liquid crystal element changes in accordance with the level of voltage applied thereon (hereinafter a voltage applied to a liquid crystal element is also referred to as “a display voltage”). The display panel of a liquid crystal display apparatus is formed with pixels each having a liquid crystal element. Each pixel is applied a display voltage during a scanning period that is cyclically provided in accordance with a prescribed scanning cycle.
Each pixel in a non-scanning period retains the display voltage that is applied during a scanning period to provide the luminance corresponding to that retained voltage. For each pixel, a non-scanning period for retaining a data (a display voltage) is overwhelmingly longer than a scanning period for being written a data, i.e., being applied with a display voltage. For instance, for each pixel in a liquid crystal display apparatus with 200 scanning lines, a non-scanning period will be 200 times longer than a scanning period. Hence, the display voltage retentivity (data retentivity) in each pixel is significant, since lower display voltage retentivity requires a scan at higher frequencies, increasing the power consumption.
Generally, pixels are arranged on a glass substrate or a semiconductor substrate using a TFT (Thin Film Transistor) element or the like. Therefore, the display voltage retentivity above may be degraded when the level of retained display voltage decreases due to a leakage current occurring in the TFT element in a non-scanning period.
A configuration for suppressing such a leakage current during a non-scanning period is disclosed, for example, in Japanese Patent Laying-Open No. 5-127619, in which a plurality of TFT elements are connected in series in each pixel to divide a voltage applied on the TFT elements (source-drain voltage).
However, even with the pixel configuration shown in Japanese Patent Laying-Open No. 5-127619, it is difficult to suppress the leakage current at higher display voltages. Another known configuration involves controlling a gate voltage to forcibly reverse-bias a TFT element in a non-scanning period. In this case, since a voltage stress on a gate insulation film is large, the reliability of the gate insulation film becomes a problem.